Epitaxial materials are inherently freer of oxygen and carbon impurities than are bulk crystalline silicon wafers. They provide two unique advantages for device fabrication that cannot be achieved by other means:
Leveraging these advantages has led to the use of silicon epitaxial layers for a variety of technological requirements in semiconductor devices.
Controlled dopant profiles and abrupt dopant profile changes offer unique advantages for device design. In bipolar devices the use of epitaxial layers to control dopant profiles enables higher switching speeds, improves high voltage operation and linearity, lowers base resistance and simplifies isolation schemes. In MOS devices, the use of epitaxial layers can lower diffused-line capacitance and improve diffused-line charge retention, improve resistance to alpha particle and static charge damage and improve dynamic Random Access Memory (RAM) performance. In addition, the use of epitaxial silicon layers in CMOS devices can improve latch-up protection. Hammond notes that Vapor Phase Epitaxy (VPE) silicon makes possible many different doping profiles that are used in modern device fabrication. These include:
CMOS designs that employ a lightly doped layer of epitaxial silicon over a heavily doped substrate achieve higher breakdown voltages while simultaneously keeping collector resistance low. CMOS transistor performance has also been significantly improved through the exploitation of strain-induced band-structure modification that directly impacts carrier mobility in targeted device layers. This band engineering approach leverages the enhanced electron mobility that is observed in epitaxial Si layers that are under biaxial tensile strain as well as the enhanced hole mobility that is produced in epitaxial Si1-xGex layers under biaxial compressive strain. A more intuitive way to view the influence of lattice stress on electrical conduction is to consider the impact of stress on electrons and holes. Electrons travel through the space that divides the atoms in the crystal lattice in pseudo ballistic trajectories until they encounter an electric field. Therefore, as they move through a crystal lattice, electrons are slowed by interactions with the positive electric fields surrounding each silicon atom in the lattice. When the lattice is subjected to tensile stress, the distance between atoms in the lattice is increased and electrons have longer ballistic trajectories between interactions with lattice atoms and, hence, higher mobility. Hole mobility has the opposite relationship with stress in the crystal lattice. Hole movement in the lattice is caused by an electron moving from the outer shell of a silicon atom to the outer shell of a neighboring silicon atom that has a positive charge (the hole). Basically, the hole is filled in creating a hole in the atom that donated the electron. Compressive stress reduces the distance between neighboring silicon atoms making this transfer of electron to hole easier and, in that way, increasing hole mobility. Strained epitaxial layers that are created through the use of juxtaposed Si and Si1-xGex epitaxial layers are used in the source and drain regions in advanced CMOS transistors. Channel layers in these devices also use epitaxial strained layers.
CVD epitaxy, also known as VPE, is the technology of choice for both homoepitaxial and heteroepitaxial processes for semiconductor device fabrication. Figure 4 shows a schematic representation of a typical VPE deposition process (for an As-doped n-epitaxial Si layer) on a wafer surface. Typically, silicon epitaxial processes are carried out at atmospheric pressure using a high flow of hydrogen carrier gas. Si1-xGex epitaxial processes differ from silicon epitaxy in that they are much more sensitive to ambient contaminants such as oxygen. Special care must be taken in these processes to employ point-of-use ultra-purification of the feed gases and/or to process under ultra-high vacuum (UHV) conditions. In addition, Si1-xGex processes are performed at significantly lower temperatures than silicon epitaxy. Recently, silicon carbide epitaxial layers have become of interest for device makers. These are higher temperature processes, running 300°C - 400°C hotter than silicon epitaxy processes.
|Device Type||Thickness (microns)||Resistivity (ohm-cm)|
|Bipolar Discrete Devices|
|Bipolar Integrated Circuits|
Table 1. Silicon Epitaxial layers, applications and specifications.
The chemical reactions used for the production of undoped and doped epitaxial silicon and Si1-xGex include:
A high co-flow of hydrogen carrier gas during the epitaxial layer deposition process helps to keep the concentration of elemental reactants on the substrate surface low enough to promote ordered crystal growth; it also helps to avoid particle-producing gas phase reactions. Silicon homoepitaxial processes that employ chlorosilane precursors and temperatures in excess of 1000°C have growth rates that range between 0.2 and 2.0 µm/min, depending on the process conditions. Process temperatures in both homo- and heteroepitaxial processes are high enough to promote surface mobility of the adsorbed silicon, germanium and dopant atoms so that they move freely on the substrate surface until they become locked into an ordered crystal lattice site, as shown in Figure 5. In addition, high temperatures in epitaxial processes promote desorption of the reaction by-products from the substrate surface (i.e., HCl, H2) which, in turn, maintains high deposition rates and surface mobility.
The mechanistics of both homo- and heteroepitaxial process can be roughly broken down into the following steps, illustrated in Figure 4:
Thin Film Deposition