CMOS Wafer Processing

Pad Oxide (Thermal Oxidation)

The initial step in the CMOS process is the formation of a "pad" thermal silicon dioxide layer on the wafer surface. The pad oxide relieves stress between the substrate and the subsequent silicon nitride layer (see below), diminishing stress-induced dislocations in the substrate (thick nitride layers can induce such dislocations). Silicon dioxide's excellent electrical properties and the fact that thin films of the material can be formed by direct oxidation of the substrate have made thermal silicon dioxide the primary insulating film material employed in semiconductor device manufacture. Thermal oxides have high electrical resistivity (>1020 Ω-cm), a high energy band gap (~9 eV) and a high breakdown field strength (>10 MV/cm). The films exhibit conformal growth on exposed silicon surfaces and, when grown on H-passivated silicon surfaces, have extremely regular, stable and reproducible Si/SiO2 interfaces. Their high etch selectivity with HF is also a very desirable characteristic in device manufacturing processes.

Pad oxides are 10 - 50 nm thick, typically grown using a "dry" oxidation process:

Si + O2 → SiO2

Dry oxidations are performed at temperatures ranging from 900°C to 1200°C at high oxygen pressures. Dry oxidation processes exhibit relatively low oxide growth rates when compared against other thermal oxidation processes, typically around 14 - 25 nm/hr. Because of this, dry oxidation processes are normally used only when silicon dioxide film thicknesses of less than 100 nm are needed. In general, dry oxidation processes produce silicon dioxide films with the highest quality electrical and material characteristics.

Thermal silicon dioxide films can also be produced using the reaction of the substrate with steam in what is known as a "wet" oxidation. Wet oxidations can be performed using entrained water:

Si + 2H2O → SiO2 + 2H2 or using the in situ generation of steam through the reaction of hydrogen and water:

2H2 + O2 → 2H2O + Si → SiO2 + 2H2

See Thermal Oxidation for a more detailed discussion thermal oxidation processes.

Silicon Nitride

The next step is the deposition of a layer of silicon nitride over the pad oxide. This layer acts as a stop for the chemical mechanical polishing (CMP) step later in the process. Silicon nitride thin films can be deposited by Low Pressure Chemical Vapor Deposition (LPCVD) using the chemical reaction:

3SiH2Cl2 + 10NH3 → Si3N4 + 6NH4Cl + 6H2

The equipment and processes employed for silicon nitride and other LPCVD thin films are described in greater detail in Low Pressure Chemical Vapor Deposition Systems.

Shallow Trench Isolation (STI) Process

In a CMOS device, shallow trenches filled with silicon dioxide are used to electrically isolate the n- and p-type active areas on the substrate surface. The following procedure is used to create these trenches in technologies below 300 nm.

The silicon nitride layer is patterned using a photolithography process. The first step in photolithography is the deposition of a layer of photoresist. Photoresists are light sensitive organic materials that become either more (positive resist) or less (negative resist) soluble in selected solvents on exposure to appropriate wavelengths of light. In the first step of the STI process, a photoresist layer is deposited on the silicon nitride using a method known as spin coating. In this process the substrate is rotated at a high angular velocity (up to 5000 rpm) while a viscous liquid solution of the photoresist is dispensed onto the center of the substrate. Centrifugal force drives the photoresist solution to the edges of the substrate and a layer of photoresist with a very uniform thickness across the substrate is deposited on the surface. The target thickness of the layer varies, depending on the particular CMOS process. Following formation of the photoresist layer, the substrate is subjected to a "soft bake" at an elevated temperature that removes the solvent in which the photoresist was dissolved. Once the photoresist layer has dried, it is patterned using light exposure. Typically, CMOS processes use ultraviolet (UV) light and step-and-repeat patterning using a tool called a "stepper". After exposure, the substrate, with resist, is subjected to another bake step that further hardens the photoresist layer that remains behind in the unexposed regions. Next, the substrate undergoes a development step that dissolves away the photoresist in the exposed areas, forming the desired pattern in the photoresist mask on the silicon nitride layer. Advanced patterning tools and the photolithography process in general are described in detail in Semiconductor Lithography.

Once the mask has been formed, the isolation trenches can be created. This is done by etching the trench into the substrate, then backfilling the trench with deposited silicon dioxide. The substrate with its masking photoresist and underlying silicon nitride layers first undergoes a plasma etch process to remove material in those areas not covered by photoresist (silicon nitride, pad oxide and epitaxial silicon), creating the isolation trenches. A sequential series of plasma etch chemistries is required to remove these different materials. The silicon nitride layer is removed using a fluorine atom etch that employs sulfur hexafluoride as the fluorine source. The pad oxide layer is removed using a fluorine atom etch that employs carbon tetrafluoride as the source gas. Finally, the silicon in the epitaxial layer is removed using a mixture of difluoroethylene and sulfur hexafluoride as the fluorine atom source. The reasons for these different chemistries rests in the need to optimize the etch rates and etch directionality for each individual layer being removed in the trench formation process. Etch processes are described in Semiconductor Etching.

Following trench formation, the photoresist layer is removed in a plasma ashing step (see Wet Substrate Surface Cleaning) and a wet clean is performed that leaves a passivated silicon surface in the trenches (typically an RCA clean incorporating piranha, SC-1, SC-2 and DHF). A trench liner of thermal silicon dioxide is grown on the exposed epitaxial silicon within the trench, followed by a trench filling oxide deposition step in which an organometallic silicon source (tetraethoxysilane, TEOS, Si(OC2H5)4) is reacted with ozone, O3, in a high density plasma deposition process known as HDP-CVD to deposit undoped silicon dioxide in the trenches. The process characteristics and equipment requirements for TEOS-Oxides and HDP-CVD are discussed in detail in Thin Film Deposition.

The final step in the STI process is the use of chemical mechanical polishing (CMP - see Chemical Mechanical Planarization) to planarize and polish the surface. In this step, the purpose of the silicon nitride layer becomes apparent as the much greater hardness of the nitride allows it to act as a stop that prevents the CMP process from removing the TEOS-oxide in the shallow trenches. Following the CMP process, the remaining nitride is stripped off selectively using phosphoric acid (H3PO4) at 140°C and the pad oxide removed using HF. A new layer of thermal oxide is then grown on the substrate surface using dry oxidation.

N- and P-Well Process

The next step in the CMOS process flow is the formation of the active area n- and p-wells. These wells are formed in the open substrate surface areas defined by the shallow trenches. In the first step of well formation, a photoresist is deposited and patterned (as described above) so that the n-well area is masked and the p-well area is exposed. The substrate then undergoes an ion implantation process to deposit boron into the substrate in the exposed p-well area. In the ion implantation process, a boron (or phosphorus) source is first ionized under high vacuum conditions to create 11B+ ions in the gas phase. The source can be a solid target or a gaseous boron compound, depending on the equipment used. The 11B+ ions are passed through a magnetic field analyzer that eliminates any contaminating ionic species before being accelerated using electromagnetic fields to a selected energy. The substrate to be implanted is located in a process chamber at the end of the ion acceleration column and it undergoes ion bombardment by the 11B+ ions coming out of the acceleration column. The 11B+ ions penetrate into the silicon substrate to a depth that is dependent on the energy imparted to them in the accelerating column. The final position and concentration of dopant atoms in the substrate is dependent on the ion energy and exposure time, respectively. In modern CMOS devices, different ion energies are employed to create zones in the substrate that have different dopant concentrations at different depths. Following p-well ion implantation, the n-well for the device is created in a similar manner. The final step in well formation is a rapid thermal anneal of the substrate that removes any lattice damage that may have occurred in the implantation process and establishes a continuous vertical dopant concentration profile in the well. Ion implantation equipment and processes are described in detail in Ion Implantation. It should also be noted that certain modern device technologies employ in situ doped layers to avoid the need for ion implantion.

Gate Process

The first step in the gate formation process is an RCA strip and clean (incorporating piranha, SC-1, SC-2 and DHF) that removes any residual contamination and the thin thermal oxide layer, leaving a hydrogen-passivated silicon surface. Following this, a thin dielectric layer that will become the gate oxide is grown on the exposed silicon in the well areas. Older device structures employed a thermal oxide layer for this purpose; however, as devices shrank in size and the gate oxide layer became ever thinner to accommodate lower gate voltage, leakage due to quantum tunneling of electrons through the gate oxide became a serious problem. For this reason, more advanced CMOS devices use multilayer gate oxide structures that employ barrier layers and high dielectric constant (high-k) materials. High-k materials achieve greater electrical fields in the substrate at higher physical oxide thickness than can be achieved using silicon dioxide. The greater physical thickness of the gate prevents quantum tunneling and excessive leakage. For the purpose of describing the CMOS process flow, we will assume the simpler case in which silicon dioxide is suitable for gate formation. The silicon dioxide gate oxide layer is grown, typically to a layer thickness of 5-10 nm, using a thermal oxidation process that is made more controllable through the use of slower oxidizers than oxygen, e.g., nitrous oxide, N2O, as the oxidizing agent.

The next step in the gate process is the formation of the gate electrode using highly doped polycrystalline silicon. First, an undoped polysilicon layer (400 - 500 nm) is deposited over the gate oxide on the substrate. Polysilicon is usually deposited using a LPCVD process carried out at 200 - 300 mTorr and 600°C - 620°C. In advanced devices, a barrier layer such as TiN may be deposited on the oxide prior to the polysilicon deposition. Barrier layers are employed in advanced device structures to reduce or eliminate impurity diffusion from the polysilicon into the gate oxide. Polysilicon properties and processes, and LPCVD processes and equipment are described in detail in Thin Film Deposition. The substrate is next coated with photoresist, and the resist is patterned and developed to define the gate structure in the active areas. Using a plasma etch process that employs fluoride-based chemistry (i.e., CF4, CH2F2, SF6, etc.), the polysilicon layer is etched away except in those areas protected by the photoresist. Following the polysilicon etch process, the substrate undergoes a plasma ashing step to remove the photoresist. The polysilicon is then oxidized in a thermal oxidation process, forming a layer of oxide surrounding the polysilicon core of the gate structure. Next, a layer of LPCVD silicon nitride is deposited over the gate structure, followed by a plasma etch of the nitride layer that leaves nitride side-wall spacers on either side of the polysilicon gate. This structure is subjected to an ion implant process in which the polysilicon gate is heavily implanted with phosphorus to increase its electrical conductivity. Variations on the ion implant process flow are used to form lightly doped drain and source regions under the sidewalls, but these are not included in this discussion in order to simplify the presentation of fabrication principles. The ion implant process creates the n+ and p+ source/drain regions in the P-well and N-well, respectively. A piranha clean is then performed to remove any remaining photoresist residues.

Contact Process

The substrate undergoes a short (~ 1 min) oxide etch using buffered oxide etch (BOE) that removes the thermal oxide from the top of the polysilicon gate and from the surfaces of the source and drain regions in the substrate. A sputtering process is used to deposit a layer of titanium over the gate, source and drain areas. This is followed by a rapid thermal process that converts the areas where titanium is in contact with silicon to titanium silicide, TiSi2, i.e., the top layers of the gate, source and drain. The titanium layer is then etched in sulfuric acid, removing any remaining elemental titanium but leaving behind the TiSi2. Titanium silicide improves the ohmic contact between metallization and the gate, source and drain. It should be noted that some processes use metal gates or add gates at the end of the device fabrication process (gate last processes).

The next step in this process is the deposition of a SiO2 dielectric layer using a TEOS-CVD process. The TEOS-oxide process is chosen for this layer due to excellent step coverage characteristics that allow it to conformally cover the gate structure. The TEOS-oxide dielectric layer is then patterned and etched to open contact holes to the source/drain regions followed by an RCA clean to remove photoresist residues. Next, Tungsten is sputter deposited and is the first metal layer. The tungsten layer is patterned using photolithography so that the source/drain contacts are protected by PR while the tungsten/TEOS-oxide layer on top of the gate is exposed. The tungsten is then etched away using a reactive ion etch. While it is not evident in the accompanying cross-sections, the contact to the gate is also created in this segment of the process.

A TEOS-based CVD process is used to deposit a second layer of dielectric, commonly referred to as an intermetal dielectric. This dielectric layer is patterned using a conventional photolithography process to create contact holes to the first level metal which contacts the source/drain regions. A sputter deposition process and photolithography are employed to deposit and pattern an aluminum-copper alloy in this second-level metal process.

In summary, the CMOS structure is complete and forms the building blocks for complex IC structures.