The word lithography comes from the greek words for stone (lithos), and to write (graphia). In semiconductor device manufacturing, the stone is the silicon wafer and the ink is the deposition, lithography, and etch process that creates the desired feature. Since lithography for semiconductor device manufactureing involves the use of optical exposure to create the pattern, semiconductor lithography is commonly called "photolithography".
Redistribution Layers (RDL), Under Bump Metallization (UBM) and bump and pillar formation are key processes enabling high density interconnects used in 2.5D and 3D advanced packaging. In order to meet the quality and high throughput needs of the industry, the wafer stage must step and settle quickly with limited vibration transference to flash illumination optics. The stage must function with little process variability in absolute accuracy and be repeatable within a small process window due to stacking of multiple lithography layers on the same die. This level of accuracy and repeatability is needed from die to die within a single wafer and from machine to machine on the manufacturing floor to ensure high quality ICs.
Challenges specific to lithography include:
Lithography uses a step, settle, and illuminate process to create features used in 2.5D and 3D advanced packages. These process steps are repeated on a single die to create multilayer features, die to die on a single wafer, wafer to wafer on the same machine and ultimately machine to machine on the manufacturing floor.
High Accuracy Motion
The complex 2.5D and 3D structures of advanced packages require multiple reticles and a significant increase in the number of exposures to build up the structures which can reduce process throughput. One way the industry has tried to mitigate lower throughput is by increasing die size, resulting in a reduction of elapsed lithography time by processing fewer die per wafer. However, larger sized die require a greater degree of positioning accuracy on the surface. Our advanced Z Tip Tilt (ZTT) and theta stage with high accuracy and dynamic capabilities enable perfect alignment and accuracy between the die and the die surface. The ZTT stage provides autofocus capability to dynamically maintain the wafer in the correct Z position. These capabilities support using larger die in advanced packages by resolving the alignment and accuracy issues.
High Speed Motion
Another way to increase throughput is to increase the speed of wafer movement between flash illuminations. Our air bearing stage has a typical acceleration of 1-2 g with a jerk time of a few milliseconds for moving masses in the XY direction. Quick movement over a short distance can create oscillation of the optics column resulting in illumination delays as the wafer settles. Our motion control system provides quick step and settle of the stage while simultaneously managing the active isolation and synchronizing it with the stage’s motion profile to avoid base motion as well as residual acceleration. The fast stage movement speed and limited vibration transference to the flash illumination optics enables an overall faster processing time resolving the throughput issue.
The lithography process requires precision, accuracy and repeatability wafer to wafer and machine to machine to ensure end device reliability. Without repeatedly precise, accurate positioning of features, multiple die cannot be stacked and interconnected to create a fully functioning and reliable device. Our lithography motion control solutions provide a high level of movement accuracy and repeatability, within ±100 nm on a 300 mm wafer, within a defined process window. Our strong metrology capabilities allow us to calibrate stages with a high degree of accuracy, increasing the reliability of our stages through stable and high positioning repeatability. This high level of repeatability within a small area supports multilayer build-up of 3D structures without negatively impacting yield of stacked devices. This also ensures the same level of accuracy can be achieved wafer to wafer and machine to machine removing any yield concerns due to incorrect positioning of 2.5D and 3D structures.
The adoption of panel processing is another way the industry is trying to increase advanced packaging throughput. In response to this changing dynamic, we have developed the DynamYX® DATUM® stage capable of supporting 500 mm panel sizes with similar step and settle, vibration isolation and positioning accuracy and repeatability.
Nanoimprint lithography is an alternate method for creating advanced packaging structures which uses a dispensed resist or liquid which is then stamped and UV cured. For this alternate process, absolute accuracy is not as critical because the process uses fiducial markings to enable adjustment to the proper location. Instead, due to the forces of the stamping process, stiffness of the surface is important to ensure there is no warp of the stamped features. DATUM stages provide the level of stiffness needed to ensure good imprint of the structures on the die. The DATUM stage uses the same fast step and settle technology to ensure sufficient throughput.
For additional information on the semiconductor lithography process as well as other semiconductor applications please download our free Semiconductor Devices and Process Technology eBook.